State of the art microprocessor designs continue to integrate operation-specific execution units (e.g. pixel-processing units, floating-point dividers and multipliers) on a single chip. Since these operation-specific execution units are tuned to perform specific tasks, their use typically improves a microprocessor's overall performance. The drive for higher performance is especially evident in floating point computations, and typically, superior floating-point performance is key to microprocessor competitiveness. Among the problems associated with floating point computations is improving the performance of a floating point comparison operation, while simultaneously minimizing the logic circuitry required to implement floating-point instructions (e.g. floating-point add and subtract) in an execution unit.
A floating point comparison operation establishes the ordering of two numbers. Traditionally, floating-point comparison operations have been implemented along with floating-point add and subtract operations. It is not necessary, however, that floating-point comparison operations be performed in the execution unit where the addition and subtraction is performed. Traditional implementations perform a comparison of two floating point numbers (A and B) by first subtracting the exponents of the two floating point numbers to be compared. Using exponent flags, the execution unit then determines which floating-point number (A or B) has the larger exponent. Based upon such determination, the execution unit then decides to align either floating-point A or floating-point B so that the exponents are equal. The floating-point execution unit aligns the floating-point number with the smaller exponent by performing a right shift by a number of bit positions equivalent in magnitude to the exponent difference. Subsequent thereto, the floating-point execution unit executes a subtraction of the mantissas to determine which, if either, of the floating-point numbers is larger. Generally, in the first technique, additional logic is required to determine equivalency between the exponents and the mantissas. Such additional logic determines a zero result from the exponent and mantissa subtraction operations. Accordingly, the microprocessor generates a comparison result, which may be in the form of a set of conditions codes, or as a true/false response to a set of predicates.
In the first technique, the floating-point comparison result is essentially a floating-point subtraction operation, and essentially, the floating-point comparison is performed using the same hardware employed to perform other floating-point operations (e.g. subtraction). Consequently, the generation of the floating-point comparison result, may take a significant amount of time or cycles depending upon the floating-point execution unit's structure. The floating-point comparison operation has a latency equal in clock cycles to the latency of the floating-point operations. Thus, a disadvantage of the first technique is that the floating-point comparison may be slower than necessary since performance of the comparison operation is tied to the execution unit's structure and/or partitioning.
In U.S. Pat. No. 4,858,166, a second technique for generating a floating-point comparison result is disclosed. In the '166 patent, the execution unit subtracts the exponents of the two floating point numbers (A and B) to be compared. The execution unit then determines if the result of the subtraction is zero. If the result is not zero, the execution unit compares the signs of the mantissas and the result of the comparison of the exponents to determine which floating-point number A or B is greater. If the result of the exponent comparison is zero, then the exponents of the floating point numbers A and B are equal. The execution unit then determines if the signs of A and B are equal. If so, then the execution unit performs a subtraction of the mantissas to determine the larger of the numbers A or B. If the signs are not equal, then the positive number (A or B)is the larger.
Accordingly, the '166 patent discloses a floating-point comparison method which uses exponent subtraction and a resulting difference signal (overflow signal from the exponent subtraction), exponents-equal detection, mantissa subtraction and the resulting difference signal, and mantissas-equal detection to order two floating-point numbers. The advantages of the second technique over the first is the faster execution time gained by immediately performing the mantissa subtraction along with the exponent subtraction, with no alignment being performed on the mantissas themselves. Essentially, if the exponents are different, the result of the mantissa subtraction is meaningless, and only the exponents and the sign bits are required to order the numbers. If the exponents happen to be the same, then no alignment of the manassas is necessary, and the mantissa subtraction result along with the sign bits determine the ordering of the two numbers.
Accordingly, the second technique attempts to speed-up the comparison execution time by bypassing the alignment step. A disadvantage of the second technique is the inherent requirement that the comparison operation share certain logic (e.g. exponent subtracter and mantissa subtracter) in the floating-point execution unit. Consequently, the exertion time of the floating-point comparison operation is still dependent upon a partitioning or structure which does not facilitate maximum performance. Thus, attempts to speed-up the execution time of a floating-point comparison would require duplication of large sections of logic (such as the mantissa subtracker).
Thus, it is desirable to provide a method for performing a floating-point comparison which maximizes performance, while minimizing the necessary logic required for implementation of the method.